Invention Grant
- Patent Title: Systems and methods for wafer alignment
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Application No.: US16046201Application Date: 2018-07-26
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Publication No.: US10242901B2Publication Date: 2019-03-26
- Inventor: Yang Chao , Keith E. Ypma , Steve J. Strauch
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/68
- IPC: H01L21/68 ; G03F7/20 ; G03F9/00 ; G01B11/14

Abstract:
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
Public/Granted literature
- US20180330976A1 SYSTEMS AND METHODS FOR WAFER ALIGNMENT Public/Granted day:2018-11-15
Information query
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