公开(公告)号：US10062595B2

公开(公告)日：2018-08-28

申请号：US15657298

申请日：2017-07-24

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F9/00 ,  G01B11/14 ,  G03F7/20

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US09741612B2

公开(公告)日：2017-08-22

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L23/544 ,  H01L21/683 ,  H01L23/48 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US10347519B2

公开(公告)日：2019-07-09

申请号：US16248500

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: G03F7/20 ,  G03F9/00 ,  G01B11/14 ,  H01L21/68

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the water based on the comparison.

公开(公告)号：US20190148202A1

公开(公告)日：2019-05-16

申请号：US16248500

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G01B11/14 ,  G03F9/00 ,  G03F7/20

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US20180330976A1

公开(公告)日：2018-11-15

申请号：US16046201

申请日：2018-07-26

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F7/20 ,  G01B11/14 ,  G03F9/00

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US20170256501A1

公开(公告)日：2017-09-07

申请号：US15062452

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Joseph L. Hess ,  Keith E. Ypma ,  Kurt J. Bossart

IPC: H01L23/544 ,  G06T11/20 ,  H01L21/66 ,  H01L25/065 ,  H01L21/67 ,  H01L21/68 ,  H01L25/00 ,  G06T7/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G06T7/001 ,  G06T7/11 ,  G06T7/73 ,  G06T11/20 ,  G06T2207/30148 ,  G06T2207/30204 ,  H01L21/67259 ,  H01L21/681 ,  H01L22/12 ,  H01L22/20 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level. Related methods of forming a semiconductor wafer, semiconductor assembles and metrology tools for use in implementing the methods are disclosed.

公开(公告)号：US09754895B1

公开(公告)日：2017-09-05

申请号：US15062452

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Joseph L. Hess ,  Keith E. Ypma ,  Kurt J. Bossart

IPC: G02F1/1333 ,  H01J9/20 ,  H01L23/544 ,  G06T7/00 ,  G06T11/20 ,  H01L21/66 ,  H01L23/48 ,  H01L21/67 ,  H01L21/68 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G06T7/001 ,  G06T7/11 ,  G06T7/73 ,  G06T11/20 ,  G06T2207/30148 ,  G06T2207/30204 ,  H01L21/67259 ,  H01L21/681 ,  H01L22/12 ,  H01L22/20 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level. Related methods of forming a semiconductor wafer, semiconductor assembles and metrology tools for use in implementing the methods are disclosed.

公开(公告)号：US20170352563A1

公开(公告)日：2017-12-07

申请号：US15657298

申请日：2017-07-24

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F7/20 ,  G01B11/14 ,  G03F9/00

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US09748128B1

公开(公告)日：2017-08-29

申请号：US15170517

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F9/00 ,  G03F7/20 ,  G01B11/14

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US10600667B2

公开(公告)日：2020-03-24

申请号：US16421340

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G01B11/14 ,  G03F7/20 ,  G03F9/00

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.