公开(公告)号：US10062595B2

公开(公告)日：2018-08-28

申请号：US15657298

申请日：2017-07-24

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F9/00 ,  G01B11/14 ,  G03F7/20

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US20170352563A1

公开(公告)日：2017-12-07

申请号：US15657298

申请日：2017-07-24

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F7/20 ,  G01B11/14 ,  G03F9/00

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US09748128B1

公开(公告)日：2017-08-29

申请号：US15170517

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F9/00 ,  G03F7/20 ,  G01B11/14

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US10347519B2

公开(公告)日：2019-07-09

申请号：US16248500

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: G03F7/20 ,  G03F9/00 ,  G01B11/14 ,  H01L21/68

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the water based on the comparison.

公开(公告)号：US20190148202A1

公开(公告)日：2019-05-16

申请号：US16248500

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G01B11/14 ,  G03F9/00 ,  G03F7/20

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US20180330976A1

公开(公告)日：2018-11-15

申请号：US16046201

申请日：2018-07-26

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F7/20 ,  G01B11/14 ,  G03F9/00

CPC classification number: H01L21/681 ,  B65G2203/0233 ,  B65G2203/041 ,  B65G2811/0626 ,  G01B11/14 ,  G03F7/70633 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7007 ,  G03F9/7015 ,  G03F9/7088

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US10600667B2

公开(公告)日：2020-03-24

申请号：US16421340

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G01B11/14 ,  G03F7/20 ,  G03F9/00

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US20190279892A1

公开(公告)日：2019-09-12

申请号：US16421340

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G01B11/14 ,  G03F9/00 ,  G03F7/20

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US10242901B2

公开(公告)日：2019-03-26

申请号：US16046201

申请日：2018-07-26

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F7/20 ,  G03F9/00 ,  G01B11/14

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.