- Patent Title: SOI wafers with buried dielectric layers to prevent CU diffusion
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Application No.: US15713756Application Date: 2017-09-25
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Publication No.: US10242947B2Publication Date: 2019-03-26
- Inventor: Anthony K. Stamper , Mukta G. Farooq , John A. Fitzsimmons
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent David Cain
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L23/532 ; H01L21/762 ; H01L21/768 ; H01L23/00 ; H01L23/48 ; H01L23/522

Abstract:
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.
Public/Granted literature
- US20180012845A1 SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION Public/Granted day:2018-01-11
Information query
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