公开(公告)号：US20180218991A1

公开(公告)日：2018-08-02

申请号：US15420362

申请日：2017-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Tanya A. Atanasova

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/11013 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014

Abstract: The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. The method may include: forming a metallic pillar over a substrate, the metallic pillar having an upper surface; forming a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and forming a solder material over the upper surface of the metallic pillar within and constrained by the wetting inhibitor layer.

公开(公告)号：US20180108566A1

公开(公告)日：2018-04-19

申请号：US15837279

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/498 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

公开(公告)号：US20180053743A1

公开(公告)日：2018-02-22

申请号：US15239976

申请日：2016-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D. W. Melville ,  Mukta G. Farooq

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L27/0694 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

公开(公告)号：US09818637B2

公开(公告)日：2017-11-14

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US09461017B1

公开(公告)日：2016-10-04

申请号：US14685061

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Andrew H. Simon ,  Anthony K. Stamper

IPC: H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/66 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/66 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/8112 ,  H01L2224/8312 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14

Abstract: An electronic package comprising a plurality of vertically stacked integrated circuit (IC) devices including a first IC device and a second IC device is provided. The electronic package also includes a first bonding layer coupling one side of the first IC device entirely to a portion of a side of the second IC device. The remaining portion of the side of the second IC device that is not coupled to the one side of the first IC device, includes an antenna.

Abstract translation: 提供了一种包括多个垂直堆叠集成电路（IC）装置的电子封装，包括第一IC器件和第二IC器件。 电子封装还包括将第一IC器件的一侧完全耦合到第二IC器件的一侧的一部分的第一接合层。 第二IC器件的未耦合到第一IC器件的一侧的侧面的剩余部分包括天线。

公开(公告)号：US10388567B2

公开(公告)日：2019-08-20

申请号：US15724493

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Mukta G. Farooq ,  Carole D. Graas ,  Xiao Hu Liu

IPC: H01L21/768 ,  H01L23/48

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

公开(公告)号：US09892970B2

公开(公告)日：2018-02-13

申请号：US15171314

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/498 ,  H01L21/3065

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

公开(公告)号：US20170352592A1

公开(公告)日：2017-12-07

申请号：US15171314

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/311 ,  H01L49/02 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

公开(公告)号：US09728506B2

公开(公告)日：2017-08-08

申请号：US14957860

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Joyce C. Liu ,  Jennifer A. Oakley

IPC: H01L23/52 ,  H01L23/538 ,  H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/762 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0642

Abstract: Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.

公开(公告)号：US20170186643A1

公开(公告)日：2017-06-29

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.