Invention Grant
- Patent Title: Method for polishing semiconductor substrate
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Application No.: US15129842Application Date: 2015-03-30
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Publication No.: US10249486B2Publication Date: 2019-04-02
- Inventor: Masashi Teramoto , Tatsuya Nakauchi , Noriaki Sugita , Shinichi Haba , Akiko Miyamoto
- Applicant: NITTA HAAS INCORPORATED
- Applicant Address: JP Osaka
- Assignee: NITTA HAAS INCORPORATED
- Current Assignee: NITTA HAAS INCORPORATED
- Current Assignee Address: JP Osaka
- Agency: Clark & Brody
- Priority: JP2014-073797 20140331
- International Application: PCT/JP2015/059925 WO 20150330
- International Announcement: WO2015/152152 WO 20151008
- Main IPC: H01L21/02
- IPC: H01L21/02
Abstract:
Proposed is a method for polishing a semiconductor substrate including an intermediate polishing step of polishing in such a way that the number of surface defects having heights of less than 3 nm is 45% or more of the total number of the surface defects on the surface of a semiconductor substrate, and a final polishing step of finish-polishing the semiconductor substrate after the intermediate polishing step.
Public/Granted literature
- US20170178888A1 METHOD FOR POLISHING SEMICONDUCTOR SUBSTRATE Public/Granted day:2017-06-22
Information query
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