Invention Grant
- Patent Title: Integrated circuit package having wirebonded multi-die stack
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Application No.: US15915769Application Date: 2018-03-08
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Publication No.: US10249598B2Publication Date: 2019-04-02
- Inventor: Thorsten Meyer , Pauli Jaervinen , Richard Patten
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/49 ; H01L25/07 ; H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L23/48 ; H01L23/528 ; H01L25/00

Abstract:
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
Public/Granted literature
- US20180197840A1 INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK Public/Granted day:2018-07-12
Information query
IPC分类: