公开(公告)号：US20250167180A1

公开(公告)日：2025-05-22

申请号：US19033078

申请日：2025-01-21

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L25/00 ,  H01L25/07

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US10249598B2

公开(公告)日：2019-04-02

申请号：US15915769

申请日：2018-03-08

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US12237305B2

公开(公告)日：2025-02-25

申请号：US17958298

申请日：2022-09-30

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L25/00 ,  H01L25/07

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US20180315737A1

公开(公告)日：2018-11-01

申请号：US16029188

申请日：2018-07-06

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/07 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US20230023328A1

公开(公告)日：2023-01-26

申请号：US17958298

申请日：2022-09-30

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/49 ,  H01L21/56 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US10319688B2

公开(公告)日：2019-06-11

申请号：US14361625

申请日：2013-12-09

Applicant: INTEL CORPORATION

Inventor： Andreas Wolter ,  Saravana Maruthamuthu ,  Mikael Knudsen ,  Thorsten Meyer ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01Q1/38 ,  H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01Q1/50 ,  H01Q1/52 ,  H01L23/29

Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.

公开(公告)号：US20180197840A1

公开(公告)日：2018-07-12

申请号：US15915769

申请日：2018-03-08

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US09972601B2

公开(公告)日：2018-05-15

申请号：US14768209

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US20160276311A1

公开(公告)日：2016-09-22

申请号：US14768209

申请日：2014-08-26

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/528 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括至少部分地嵌入第一封装层中的第一裸片和至少部分地嵌入第二封装层中的第二裸片。 第一管芯可以具有设置在第一封装层的第一侧的第一多个管芯级互连结构。 IC封装还可以包括至少部分地嵌入在第一封装层中并被配置为在第一封装层的第一和第二侧之间路由电信号的多个电路由特征。 第二侧可以布置成与第一侧相对。 第二管芯可以具有第二多个管芯级互连结构，其可以通过接合引线与多个电路径特征的至少一个子集电耦合。

公开(公告)号：US20160240492A1

公开(公告)日：2016-08-18

申请号：US14361625

申请日：2013-12-09

Applicant: INTEL CORPORATION

Inventor： Andreas Wolter ,  Saravana Maruthamuthu ,  Mikael Knudsen ,  Meyer Thorsten ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01L23/66 ,  H01Q1/50 ,  H01Q1/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01Q1/38 ,  H01L23/48

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01Q1/38 ,  H01Q1/50 ,  H01Q1/526 ,  H01L2924/00

Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.

Abstract translation: 在可用于封装模具的陶瓷上描述天线。 在一个示例中，封装具有管芯，管芯上的陶瓷衬底，附着到陶瓷衬底的天线以及将天线电连接到管芯的导电引线。