Invention Grant
- Patent Title: Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices
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Application No.: US15627835Application Date: 2017-06-20
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Publication No.: US10249616B2Publication Date: 2019-04-02
- Inventor: Hui Zang , Manfred Eller , Haiting Wang , Daniel Jaeger
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L21/3213 ; H01L21/8234 ; H01L27/06 ; H01L27/02 ; H01L29/66 ; H01L29/78 ; H01L29/49

Abstract:
One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.
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Information query
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