公开(公告)号：US20190295898A1

公开(公告)日：2019-09-26

申请号：US16403745

申请日：2019-05-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311

摘要： Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US10340142B1

公开(公告)日：2019-07-02

申请号：US15919119

申请日：2018-03-12

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jiehui Shu ,  Pei Liu ,  Jinping Liu

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213

摘要： At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.

公开(公告)号：US20180102291A1

公开(公告)日：2018-04-12

申请号：US15288503

申请日：2016-10-07

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco ,  Daniel Jaeger

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC分类号： H01L21/823431 ,  H01L21/02129 ,  H01L21/823481 ,  H01L27/0886

摘要： Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

公开(公告)号：US10833160B1

公开(公告)日：2020-11-10

申请号：US16386363

申请日：2019-04-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/82 ,  H01L21/033 ,  H01L21/027 ,  H01L21/306 ,  H01L29/417 ,  H01L27/088 ,  H01L29/40

摘要： Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10755982B1

公开(公告)日：2020-08-25

申请号：US16508816

申请日：2019-07-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Abu Naser M. Zainuddin ,  Wei Ma ,  Daniel Jaeger ,  Joseph Versaggi ,  Jae Gon Lee ,  Thomas Kauerauf

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/66

摘要： One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.

公开(公告)号：US10418455B2

公开(公告)日：2019-09-17

申请号：US15716287

申请日：2017-09-26

申请人： GLOBALFOUNDRIES INC.

发明人： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/092

摘要： At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US10388562B2

公开(公告)日：2019-08-20

申请号：US15678229

申请日：2017-08-16

申请人： GLOBALFOUNDRIES INC.

发明人： Haigou Huang ,  Daniel Jaeger ,  Xusheng Wu ,  Jinsheng Gao

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

摘要： A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US10269654B1

公开(公告)日：2019-04-23

申请号：US15890246

申请日：2018-02-06

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

摘要： At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10204797B1

公开(公告)日：2019-02-12

申请号：US15890210

申请日：2018-02-06

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Jessica Dechene ,  Haigou Huang

IPC分类号： H01L21/00 ,  H01L21/3105 ,  H01L21/02 ,  C23C16/36 ,  H01L21/67 ,  C23C16/56 ,  C23C16/26

摘要： The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.

公开(公告)号：US20190326408A1

公开(公告)日：2019-10-24

申请号：US16458056

申请日：2019-06-29

申请人： GLOBALFOUNDRIES INC.

发明人： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/321 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28

摘要： At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.