Invention Grant
- Patent Title: Offstate parasitic leakage reduction for tunneling field effect transistors
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Application No.: US15576468Application Date: 2015-06-27
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Publication No.: US10249742B2Publication Date: 2019-04-02
- Inventor: Van H. Le , Gilbert Dewey , Benjamin Chu-Kung , Ashish Agrawal , Matthew V. Metz , Willy Rachmady , Marc C. French , Jack T. Kavalieros , Rafael Rios , Seiyon Kim , Seung Hoon Sung , Sanaz K. Gardner , James M. Powers , Sherry R. Taft
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/038192 WO 20150627
- International Announcement: WO2017/003409 WO 20170105
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/786 ; H01L29/10

Abstract:
A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.
Public/Granted literature
- US20180158933A1 OFFSTATE PARASITIC LEAKAGE REDUCTION FOR TUNNELING FIELD EFFECT TRANSISTORS Public/Granted day:2018-06-07
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