公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

申请人： Intel Corporation

发明人： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

摘要： In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11929435B2

公开(公告)日：2024-03-12

申请号：US17899429

申请日：2022-08-30

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/78391 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684

摘要： Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

申请人： Intel Corporation

发明人： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

申请人： Intel Corporation

发明人： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

摘要： A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC分类号： H01L49/02 ,  H01L27/108

CPC分类号： H01L28/65 ,  H01L28/75 ,  H01L27/10829

摘要： Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US11367789B2

公开(公告)日：2022-06-21

申请号：US16316337

申请日：2016-09-26

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Sean T. Ma ,  Harold Kennel

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/778 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00

摘要： A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US11276755B2

公开(公告)日：2022-03-15

申请号：US16303654

申请日：2016-06-17

申请人： Intel Corporation

发明人： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

摘要： Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US20210408018A1

公开(公告)日：2021-12-30

申请号：US16914140

申请日：2020-06-26

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC分类号： H01L27/11502 ,  H01L49/02 ,  H01L27/08 ,  H01G4/008 ,  G11C11/22

摘要： An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US11152290B2

公开(公告)日：2021-10-19

申请号：US16094817

申请日：2016-06-29

申请人： Intel Corporation

发明人： Benjamin Chu-Kung ,  Van H. Le ,  Willy Rachmady ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ashish Agrawal ,  Seung Hoon Sung

IPC分类号： H01L23/498 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

摘要： A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.

公开(公告)号：US10886408B2

公开(公告)日：2021-01-05

申请号：US16327206

申请日：2016-09-29

申请人： INTEL CORPORATION

发明人： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Willy Rachmady ,  Anand S. Murthy ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L29/20 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/26 ,  H01L21/8252 ,  H01L29/16

摘要： Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.