Invention Grant
- Patent Title: Maskless air gap to prevent via punch through
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Application No.: US15744018Application Date: 2015-09-23
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Publication No.: US10256141B2Publication Date: 2019-04-09
- Inventor: Manish Chandhok , Todd R. Younkin , Eungnak Han , Jasmeet S. Chawla , Marie Krysak , Hui Jae Yoo , Tristan A. Tronic
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/051729 WO 20150923
- International Announcement: WO2017/052536 WO 20170330
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L21/768 ; H01L23/522 ; H01L23/532
Abstract:
A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
Public/Granted literature
- US20180204760A1 MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH Public/Granted day:2018-07-19
Information query
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