Invention Grant
- Patent Title: Multiple-unit semiconductor device
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Application No.: US15126204Application Date: 2015-02-12
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Publication No.: US10256224B2Publication Date: 2019-04-09
- Inventor: Masaya Isobe
- Applicant: SHARP KABUSHIKI KAISHA
- Applicant Address: JP Sakai, Osaka
- Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee Address: JP Sakai, Osaka
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JP2014-102277 20140516
- International Application: PCT/JP2015/053757 WO 20150212
- International Announcement: WO2015/174107 WO 20151119
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L21/822 ; H01L27/04 ; H03K17/687 ; H01L23/495 ; H01L29/16 ; H01L29/20 ; H01L29/778 ; H01L29/78 ; H03K17/06 ; H03K17/16
Abstract:
A multiple-unit semiconductor device (1) includes a normally-ON type first FET (11) and a normally-OFF type second FET (12) that are connected to each other in series between a first terminal and a second terminal (17 and 19). The multiple-unit semiconductor device (1) further includes a protection circuit that includes a switching element for discharge (16) connected to the second FET in parallel and a trigger circuit that is disposed between the first terminal and the second terminal (17 and 19) and causes the switching element for discharge to turn to an ON state when a surge is applied to the first terminal.
Public/Granted literature
- US20170084600A1 MULTIPLE-UNIT SEMICONDUCTOR DEVICE Public/Granted day:2017-03-23
Information query
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