Invention Grant
- Patent Title: Semiconductor structures including liners and related methods
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Application No.: US15155618Application Date: 2016-05-16
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Publication No.: US10256406B2Publication Date: 2019-04-09
- Inventor: Dale W. Collins , Andrea Gotti , F. Daniel Gealy , Tuman E. Allen , Swapnil Lengade
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.
Public/Granted literature
- US20170331036A1 SEMICONDUCTOR STRUCTURES INCLUDING LINERS AND RELATED METHODS Public/Granted day:2017-11-16
Information query
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