Invention Grant
- Patent Title: Linear masking circuits for side-channel immunization of advanced encryption standard hardware
-
Application No.: US15283000Application Date: 2016-09-30
-
Publication No.: US10256973B2Publication Date: 2019-04-09
- Inventor: Raghavan Kumar , Sanu K. Mathew , Avinash L. Varna , Vikram B. Suresh , Sudhir K. Satpathy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard, & Mughal LLP
- Main IPC: H04L9/06
- IPC: H04L9/06 ; H03K19/21 ; H04L9/00 ; G09C1/00 ; G11C19/00

Abstract:
Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.
Public/Granted literature
- US20180097618A1 LINEAR MASKING CIRCUITS FOR SIDE-CHANNEL IMMUNIZATION OF ADVANCED ENCRYPTION STANDARD HARDWARE Public/Granted day:2018-04-05
Information query