A control apparatus includes a control logic circuit that is configured to generate control signals for controlling at least two inverters (e.g., 3-phase inverters) that are coupled in parallel. The control logic circuit is configured to sample output currents present in common load terminals of the inverters, and to compare the sampled currents to generated current references. The output currents may be sampled, and/or the current references generated, at a fixed rate. Errors between the sampled currents and current references are evaluated against hysteresis dead bands around the current references. The control signals are generated based on (i) retrieved modulator output values for a selected one of the inverters and (ii) the errors as evaluated against the hysteresis dead bands. The control logic circuit may implement first and second counters for coordinating the current reference generation, sampling the output currents, retrieving the modulator output values, etc.