- Patent Title: Methods and apparatus to eliminate partial-redundant vector loads
-
Application No.: US15714606Application Date: 2017-09-25
-
Publication No.: US10268454B2Publication Date: 2019-04-23
- Inventor: Farhana Aleen Schuchman , David L. Kreitzer , Rakesh Krishnaiyer , Vyacheslav Pavlovich Zakharin , Sergey Preis , Leonardo Jose Borges , Philippe Thierry
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: G06F8/41
- IPC: G06F8/41 ; G06F8/30 ; G06F11/36

Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.
Public/Granted literature
- US20180011693A1 METHODS AND APPARATUS TO ELIMINATE PARTIAL-REDUNDANT VECTOR LOADS Public/Granted day:2018-01-11
Information query