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Patent Agency Ranking
公开(公告)号：US20160259628A1
公开(公告)日：2016-09-08
申请号：US14741160
申请日：2015-06-16
Applicant: Intel Corporation
Inventor： Farhana Aleen Schuchman , David L. Kreitzer , Rakesh Krishnaiyer , Vyacheslav Pavlovich Zakharin , Sergey Preis , Leonardo Jose Borges , Philippe Thierry
CPC classification number: G06F8/30 , G06F8/4441 , G06F8/452 , G06F11/3688
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.
Abstract translation: 公开了方法，装置，系统和制品以消除部分冗余矢量载荷。 示例性装置包括基于向量操作的负载类型将向量操作与节点组相关联的节点组。 示例性装置还包括用于标识节点组中的候选的候选标识符，候选者包括节点组的向量操作的子集。 示例性装置还包括代码优化器，用于基于候选者的特征来确定替换代码，并且将与执行替换代码相关联的估计成本与执行候选的成本相比较的阈值成本进行比较。 示例性装置还包括代码生成器，当执行替换代码的估计成本满足阈值成本时，使用替换代码生成机器代码。
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公开(公告)号：US10230817B2
公开(公告)日：2019-03-12
申请号：US14976360
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Philippe Thierry , Elmoustapha Ould-Ahmed-Vall
IPC: H04L29/08 , H04L12/911
Abstract: Systems and methods for scheduling highly-parallel applications executed by high-performance computing systems. An example processing system may comprise: a control register and a processing core, communicatively coupled to the control register. The processing core may be configured to receive a node allocation request specifying an expected running time of an application and a requested number of nodes of a cluster of nodes; determine, in view of the node allocation request and a current load on the plurality of nodes, an actual number of nodes to be allocated to the application, wherein the actual number of nodes to be allocated to the application optimizes a cluster load criterion; and notify, using the control register, the application of the actual number of nodes.
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公开(公告)号：US10268454B2
公开(公告)日：2019-04-23
申请号：US15714606
申请日：2017-09-25
Applicant: Intel Corporation
Inventor： Farhana Aleen Schuchman , David L. Kreitzer , Rakesh Krishnaiyer , Vyacheslav Pavlovich Zakharin , Sergey Preis , Leonardo Jose Borges , Philippe Thierry
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.
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公开(公告)号：US20180011693A1
公开(公告)日：2018-01-11
申请号：US15714606
申请日：2017-09-25
Applicant: Intel Corporation
Inventor： Farhana Aleen Schuchman , David L. Kreitzer , Rakesh Krishnaiyer , Vyacheslav Pavlovich Zakharin , Sergey Preis , Leonardo Jose Borges , Philippe Thierry
CPC classification number: G06F8/30 , G06F8/4441 , G06F8/452 , G06F11/3688
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.
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公开(公告)号：US09785413B2
公开(公告)日：2017-10-10
申请号：US14741160
申请日：2015-06-16
Applicant: Intel Corporation
Inventor： Farhana Aleen Schuchman , David L. Kreitzer , Rakesh Krishnaiyer , Vyacheslav Pavlovich Zakharin , Sergey Preis , Leonardo Jose Borges , Philippe Thierry
CPC classification number: G06F8/30 , G06F8/4441 , G06F8/452 , G06F11/3688
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.
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