A nonvolatile memory device includes control logic and a memory cell array. The memory cell array includes a first plane and a second plane. The control logic is configured to perform a first sub-operation on the first plane, to perform a second sub-operation on the second plane, to delay the second sub-operation as much as a reference time so that a partial section of the first sub-operation does not overlap the second sub-operation, and to variably control the reference time.