A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.