Invention Grant
- Patent Title: Integrated structures and methods of forming vertically-stacked memory cells
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Application No.: US15497009Application Date: 2017-04-25
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Publication No.: US10269819B2Publication Date: 2019-04-23
- Inventor: Hongbin Zhu , Gordon A. Haller , Charles H. Dennison , Anish A. Khandekar , Brett D. Lowe , Lining He , Brian Cleereman
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L27/11582 ; H01L27/11524 ; H01L27/1157
Abstract:
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
Public/Granted literature
- US20170229470A1 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells Public/Granted day:2017-08-10
Information query
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