公开(公告)号：US11805645B2

公开(公告)日：2023-10-31

申请号：US16542645

申请日：2019-08-16

申请人： Micron Technology, Inc.

发明人： Nicholas R. Tapias ,  Andrew Li ,  Adam W. Saxler ,  Kunal Shrotri ,  Erik R. Byers ,  Matthew J. King ,  Diem Thy N. Tran ,  Wei Yeeng Ng ,  Anish A. Khandekar

IPC分类号： H10B43/27 ,  H01L21/02 ,  H01L21/285 ,  H10B41/27

CPC分类号： H10B43/27 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/28568 ,  H10B41/27

摘要： Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11387369B2

公开(公告)日：2022-07-12

申请号：US16723259

申请日：2019-12-20

申请人： Micron Technology, Inc.

发明人： Shen Hu ,  Hung-Wei Liu ,  Xiao Li ,  Zhiqiang Xie ,  Corey Staller ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Thomas A. Figura

IPC分类号： H01L27/108 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

摘要： An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

公开(公告)号：US20210193843A1

公开(公告)日：2021-06-24

申请号：US16723259

申请日：2019-12-20

申请人： Micron Technology, Inc.

发明人： Shen Hu ,  Hung-Wei Liu ,  Xiao Li ,  Zhiqiang Xie ,  Corey Staller ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Thomas A. Figura

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

公开(公告)号：US20200251347A1

公开(公告)日：2020-08-06

申请号：US16854283

申请日：2020-04-21

申请人： Micron Technology, Inc.

发明人： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC分类号： H01L21/311 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11556

摘要： A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US20200066747A1

公开(公告)日：2020-02-27

申请号：US16111648

申请日：2018-08-24

申请人： Micron Technology, Inc.

发明人： Collin Howder ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Mark W. Kiehlbauch ,  Nancy M. Lomeli

IPC分类号： H01L27/11582 ,  H01L29/66 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

摘要： A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US20200052134A1

公开(公告)日：2020-02-13

申请号：US16659478

申请日：2019-10-21

申请人： Micron Technology, Inc.

发明人： Fei Wang ,  Kunal Shrotri ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Duo Mao ,  Zhixin Xu ,  Ee Ee Eng ,  Jie Li ,  Dong Liang

IPC分类号： H01L29/792 ,  G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/28

摘要： A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.

公开(公告)号：US10553607B1

公开(公告)日：2020-02-04

申请号：US16111648

申请日：2018-08-24

申请人： Micron Technology, Inc.

发明人： Collin Howder ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Mark W. Kiehlbauch ,  Nancy M. Lomeli

IPC分类号： H01L27/11 ,  H01L27/11582 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/027 ,  H01L21/28

摘要： A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US10388665B1

公开(公告)日：2019-08-20

申请号：US15992959

申请日：2018-05-30

申请人： Micron Technology, Inc.

发明人： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC分类号： H01L27/11582 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311

摘要： An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US10381367B2

公开(公告)日：2019-08-13

申请号：US16002075

申请日：2018-06-07

申请人： Micron Technology, Inc.

发明人： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC分类号： H01L27/11568 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11519 ,  H01L29/788

摘要： A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US10269819B2

公开(公告)日：2019-04-23

申请号：US15497009

申请日：2017-04-25

申请人： Micron Technology, Inc.

发明人： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

摘要： Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.