Invention Grant
- Patent Title: Method and apparatus for reducing threshold voltage mismatch in an integrated circuit
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Application No.: US15097861Application Date: 2016-04-13
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Publication No.: US10276390B2Publication Date: 2019-04-30
- Inventor: Min-hwa Chi , Meixiong Zhao , Kuniko Kikuta
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Stephen Scuderi
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L29/66 ; H01L29/08 ; H01L21/02 ; H01L29/49 ; H01L29/40

Abstract:
A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.
Public/Granted literature
- US20170301544A1 METHOD AND APPARATUS FOR REDUCING THRESHOLD VOLTAGE MISMATCH IN AN INTEGRATED CIRCUIT Public/Granted day:2017-10-19
Information query
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