Invention Grant
- Patent Title: Integrated circuit with tamper protection and method therefor
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Application No.: US15612841Application Date: 2017-06-02
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Publication No.: US10289840B2Publication Date: 2019-05-14
- Inventor: Javier Elenes , Sebastian Ahmed , Lars Lydersen
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: SILICON LABORATORIES INC.
- Current Assignee: SILICON LABORATORIES INC.
- Current Assignee Address: US TX Austin
- Agency: Polansky & Associates P.L.L.C.
- Agent Paul J. Polansky; Rosalynn M. Smith
- Main IPC: G06F21/55
- IPC: G06F21/55 ; G06F21/72

Abstract:
An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.
Public/Granted literature
- US20180349600A1 Integrated Circuit With Tamper Protection And Method Therefor Public/Granted day:2018-12-06
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