Invention Grant
- Patent Title: Metal-oxide-semiconductor transistor and method of forming gate layout
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Application No.: US15667633Application Date: 2017-08-03
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Publication No.: US10290718B2Publication Date: 2019-05-14
- Inventor: Shih-Yin Hsiao , Ching-Chung Yang , Wen-Fang Lee , Nien-Chung Li , Chih-Chung Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: TW104133652A 20151014
- Main IPC: H01L29/423
- IPC: H01L29/423 ; G06F17/50 ; H01L23/535 ; H01L29/06 ; H01L29/78 ; H01L29/49 ; H01L29/08 ; H01L29/66

Abstract:
A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.
Public/Granted literature
- US20170330947A1 METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING GATE LAYOUT Public/Granted day:2017-11-16
Information query
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