Invention Grant
- Patent Title: Nanowire formation methods
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Application No.: US15704982Application Date: 2017-09-14
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Publication No.: US10290768B2Publication Date: 2019-05-14
- Inventor: Srinivasa Banna , Deepak Nayak
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L31/00 ; H01L33/06 ; H01L33/00 ; H01L33/32 ; H01L33/30 ; H01L27/15 ; H01L33/42 ; H01L33/44 ; H01L33/62 ; H01L33/24

Abstract:
Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.
Public/Granted literature
- US20190081206A1 NANOWIRE FORMATION METHODS Public/Granted day:2019-03-14
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