Invention Grant
- Patent Title: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time
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Application No.: US15259633Application Date: 2016-09-08
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Publication No.: US10291211B2Publication Date: 2019-05-14
- Inventor: Stanley Seungchul Song , Seong-Ook Jung , Hanwool Jeong , Tae Woo Oh , Giridhar Nallapati , Periannan Chidambaram
- Applicant: Qualcomm Technologies, Inc. , Yonsei University, University-Industry Foundation
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03K3/356 ; H03K19/096 ; H03K3/037 ; H03K3/012 ; H03K3/017

Abstract:
Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.
Public/Granted literature
- US20180069535A1 ADAPTIVE PULSE GENERATION CIRCUITS FOR CLOCKING PULSE LATCHES WITH MINIMUM HOLD TIME Public/Granted day:2018-03-08
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