Invention Grant
- Patent Title: Low area parallel checker for multiple test patterns
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Application No.: US15797504Application Date: 2017-10-30
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Publication No.: US10302695B2Publication Date: 2019-05-28
- Inventor: Tejinder Kumar , Akshat Jain
- Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
- Applicant Address: NL Schiphol
- Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee Address: NL Schiphol
- Agency: Seed IP Law Group LLP
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177

Abstract:
Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
Public/Granted literature
- US20190128960A1 LOW AREA PARALLEL CHECKER FOR MULTIPLE TEST PATTERNS Public/Granted day:2019-05-02
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