公开(公告)号：US20180175883A1

公开(公告)日：2018-06-21

申请号：US15381516

申请日：2016-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Rakesh Malik

IPC: H03M13/09 ,  G06F11/10 ,  H03M13/00

CPC classification number: H03M13/091 ,  G06F11/1004 ,  H03M13/6505

Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.

公开(公告)号：US10222415B2

公开(公告)日：2019-03-05

申请号：US15375542

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Suchi Prabhu Tandel ,  Rakesh Malik

IPC: G01R31/317 ,  G01R31/3193

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

公开(公告)号：US10198331B2

公开(公告)日：2019-02-05

申请号：US15475277

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Rakesh Malik

IPC: G06F11/22 ,  G06F11/263 ,  G06F11/273 ,  G06F11/07

Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

公开(公告)号：US10302695B2

公开(公告)日：2019-05-28

申请号：US15797504

申请日：2017-10-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder Kumar ,  Akshat Jain

IPC: G01R31/317 ,  G01R31/3177

Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.

公开(公告)号：US20180285225A1

公开(公告)日：2018-10-04

申请号：US15475277

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Rakesh Malik

IPC: G06F11/22 ,  G06F11/263 ,  G06F11/273

CPC classification number: G06F11/221 ,  G06F11/076 ,  G06F11/263 ,  G06F11/2733

Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

公开(公告)号：US20180164370A1

公开(公告)日：2018-06-14

申请号：US15375542

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Suchi Prabhu Tandel ,  Rakesh Malik

IPC: G01R31/317 ,  G01R31/3193

CPC classification number: G01R31/31703 ,  G01R31/3171 ,  G01R31/31932 ,  G01R31/31935 ,  G11C15/00 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/0405 ,  G11C2029/2602

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

公开(公告)号：US10572440B2

公开(公告)日：2020-02-25

申请号：US15850535

申请日：2017-12-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder Kumar ,  Rathod Ronak Kishorbhai ,  Apurva Sen ,  Rakesh Malik

IPC: G06F16/90 ,  G06F15/78 ,  G06F16/903

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

公开(公告)号：US10404278B2

公开(公告)日：2019-09-03

申请号：US15381516

申请日：2016-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Rakesh Malik

IPC: H03M13/09 ,  G06F11/10 ,  H03M13/00

Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.