Invention Grant
- Patent Title: False positive detection using combining gain
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Application No.: US15453330Application Date: 2017-03-08
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Publication No.: US10313058B2Publication Date: 2019-06-04
- Inventor: Gwang-Hyun Gho , Joan Anton Olivella
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00 ; H04L1/00 ; G06F17/18 ; H04L1/20 ; H04W84/04
Abstract:
A method for detecting that a set of bits has been incorrectly decoded includes calculating a combining gain experienced during processing of the set of bits. The combining gain is compared to a threshold. A false positive signal that indicates that the set of bits has been incorrectly decoded is generated when the combining gain is less than the threshold.
Public/Granted literature
- US20180262299A1 FALSE POSITIVE DETECTION USING COMBINING GAIN Public/Granted day:2018-09-13
Information query
