Invention Grant
- Patent Title: Erasing memory cells sequentially
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Application No.: US15687581Application Date: 2017-08-28
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Publication No.: US10332601B2Publication Date: 2019-06-25
- Inventor: Aaron S. Yip
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/14 ; G11C16/26

Abstract:
Methods include applying a first voltage to channel regions of a plurality of memory cells; applying a lower second voltage to each access line of a plurality of access lines coupled to the memory cells other than a first set of access lines; applying a lower third voltage to the first set of access lines while applying the first voltage and the second voltage; determining a desired voltage level of the third voltage for a subsequent set of access lines; and applying the third voltage to the subsequent set of access lines while applying the first voltage and while applying the second voltage to each access line of the plurality of access lines other than the subsequent set of access lines. Methods further include methods of determining the desired voltage level for the third voltage for each set of access lines.
Public/Granted literature
- US20190066797A1 ERASING MEMORY CELLS Public/Granted day:2019-02-28
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