中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.034 seconds)

    MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC REGIONS
    1.
    发明申请
    MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC REGIONS 有权

    公开(公告)号：US20230134814A1

    公开(公告)日：2023-05-04

    申请号：US18147342

    申请日：2022-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

    APPARATUS FOR MEMORY CELL PROGRAMMING
    3.
    发明申请
    APPARATUS FOR MEMORY CELL PROGRAMMING 有权

    公开(公告)号：US20210358554A1

    公开(公告)日：2021-11-18

    申请号：US17443841

    申请日：2021-07-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron S. Yip

    IPC: G11C16/12 ,  G11C16/34 ,  G11C16/10

    Abstract: Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.

    Memory cell programming
    4.
    发明授权
    Memory cell programming 有权

    公开(公告)号：US11094379B1

    公开(公告)日：2021-08-17

    申请号：US16835664

    申请日：2020-03-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron S. Yip

    IPC: G11C11/56 ,  G11C16/12 ,  G11C16/34 ,  G11C16/10

    Abstract: Methods, as well as apparatus configured to perform similar methods, might include programming a plurality of memory cells to a particular data state of a plurality of data states, and, for each memory cell of the plurality of memory cells whose target data state is higher than the particular data state, determining a respective indication of a programming voltage level deemed sufficient to program that memory cell to a respective target threshold voltage corresponding to its respective target data state, and further programming that memory cell using a programming voltage level of a plurality of programming voltage levels corresponding to the respective indication of the programming voltage level deemed sufficient to program that memory cell to the respective target threshold voltage corresponding to its respective target data state.

    Memory cell programming with a program pulse having a plurality of different voltage levels
    5.
    发明授权
    Memory cell programming with a program pulse having a plurality of different voltage levels 有权

    公开(公告)号：US11043272B2

    公开(公告)日：2021-06-22

    申请号：US16516791

    申请日：2019-07-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron S. Yip

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.

    ERASING MEMORY CELLS
    6.
    发明申请
    ERASING MEMORY CELLS 审中-公开

    公开(公告)号：US20190287623A1

    公开(公告)日：2019-09-19

    申请号：US16427587

    申请日：2019-05-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron S. Yip

    IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

    Abstract: Memories having a controller configured to apply a first voltage level to channel regions of memory cells of an array of memory cells coupled to a plurality of access lines; apply a second voltage level, lower than the first voltage level, to a first access line; apply a third voltage level, lower than the second voltage level, to a second access line while applying the second voltage level to the first access line and while applying the first voltage level to the channel regions of the memory cells; and increase the voltage level applied to the second access line to the second voltage level and decrease the voltage level applied to the first access line to a fourth voltage level, lower than the second voltage level and different than the third voltage level, while applying the first voltage level to the channel regions of the memory cells.

    Access line management in a memory device
    8.
    发明授权
    Access line management in a memory device 有权
    存储设备中的接入线管理

    公开(公告)号：US09218884B2

    公开(公告)日：2015-12-22

    申请号：US14153590

    申请日：2014-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

    IPC: G11C5/14 ,  G11C16/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

    Abstract translation: 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

    Using non-segregated cells as drain-side select gates for sub-blocks in a memory device
    9.
    发明授权
    Using non-segregated cells as drain-side select gates for sub-blocks in a memory device 有权

    公开(公告)号：US12080351B2

    公开(公告)日：2024-09-03

    申请号：US17944940

    申请日：2022-09-14

    Applicant: Micron Technology, Inc.

    Inventor： Aaron S. Yip

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/34

    Abstract: Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

Patent Agency Ranking