- Patent Title: Reduced-dimension via-land structure and method of making the same
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Application No.: US15019776Application Date: 2016-02-09
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Publication No.: US10334728B2Publication Date: 2019-06-25
- Inventor: Cheng-Lin Ho , Chih-Cheng Lee , Po-Shu Peng
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K3/10 ; H05K3/40 ; H05K3/00

Abstract:
A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.
Public/Granted literature
- US20170231093A1 REDUCED-DIMENSION VIA-LAND STRUCTURE AND METHOD OF MAKING THE SAME Public/Granted day:2017-08-10
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