An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.