State retention circuit that retains data storage element state during power reduction mode
摘要:
A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.
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