公开(公告)号：US10742199B2

公开(公告)日：2020-08-11

申请号：US16416462

申请日：2019-05-20

Applicant: SILICON LABORATORIES INC.

Inventor： Thomas S. David ,  Wasim Quddus

IPC: H03K17/24 ,  H03K3/012 ,  H03K3/3562 ,  H03K3/289 ,  H03K3/356

Abstract: A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

公开(公告)号：US10340894B1

公开(公告)日：2019-07-02

申请号：US15963316

申请日：2018-04-26

Applicant: SILICON LABORATORIES INC.

Inventor： Thomas S. David ,  Wasim Quddus

IPC: H03K3/012 ,  H03K3/3562 ,  H03K17/24 ,  H03K3/289

Abstract: A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.