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    Dynamic containerized system memory protection for low-energy MCUs
    1.
    发明授权
    Dynamic containerized system memory protection for low-energy MCUs 有权

    公开(公告)号：US09984009B2

    公开(公告)日：2018-05-29

    申请号：US15008650

    申请日：2016-01-28

    Applicant: SILICON LABORATORIES INC.

    Inventor： Sebastian Ahmed ,  Thomas S. David ,  Marius Grannaes

    IPC: G06F13/36 ,  G06F12/14 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F12/1491 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/1052

    Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.

    ASYMMETRIC MEMORY
    3.
    发明申请
    ASYMMETRIC MEMORY 审中-公开

    公开(公告)号：US20170139844A1

    公开(公告)日：2017-05-18

    申请号：US14943912

    申请日：2015-11-17

    Applicant: SILICON LABORATORIES INC.

    Inventor： Paul Ivan Zavalney ,  Thomas S. David

    IPC: G06F12/14

    CPC classification number: G06F12/1441 ,  G06F12/1483 ,  G06F2212/1052

    Abstract: A computing system includes a central processing unit (CPU) connected to communicate over a bus, a memory configured to have at least three accessible memory storage areas arranged asymmetrically and a memory protection unit (MPU) that receives and controls memory access requests received from the central processing unit and from other processing devices, blocks or processes. The MPU determines, based on an identity of the device, block or process that generated the memory access request, whether to allow access based upon which memory area is being accessed and a type of access being requested. The areas of memory include read/write for secure and non-secure, read/write for secure only, and read for secure and non-secure but write only for secure.

    State retention circuit that retains data storage element state during power reduction mode
    4.
    发明授权
    State retention circuit that retains data storage element state during power reduction mode 有权

    公开(公告)号：US10742199B2

    公开(公告)日：2020-08-11

    申请号：US16416462

    申请日：2019-05-20

    Applicant: SILICON LABORATORIES INC.

    Inventor： Thomas S. David ,  Wasim Quddus

    IPC: H03K17/24 ,  H03K3/012 ,  H03K3/3562 ,  H03K3/289 ,  H03K3/356

    Abstract: A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

    ECC memory controller to detect dangling pointers
    5.
    发明授权
    ECC memory controller to detect dangling pointers 有权

    公开(公告)号：US10360104B2

    公开(公告)日：2019-07-23

    申请号：US15589217

    申请日：2017-05-08

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas S. David

    IPC: G06F11/10 ,  G06F11/08 ,  G06F12/14

    Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

    State retention circuit that retains data storage element state during power reduction mode
    6.
    发明授权
    State retention circuit that retains data storage element state during power reduction mode 有权

    公开(公告)号：US10340894B1

    公开(公告)日：2019-07-02

    申请号：US15963316

    申请日：2018-04-26

    Applicant: SILICON LABORATORIES INC.

    Inventor： Thomas S. David ,  Wasim Quddus

    IPC: H03K3/012 ,  H03K3/3562 ,  H03K17/24 ,  H03K3/289

    Abstract: A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.

    ECC memory controller supporting secure and non-secure regions
    7.
    发明授权
    ECC memory controller supporting secure and non-secure regions 有权

    公开(公告)号：US10218387B2

    公开(公告)日：2019-02-26

    申请号：US15589199

    申请日：2017-05-08

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas S. David

    IPC: H03M13/29 ,  G06F3/06 ,  G06F11/10

    Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

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