A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.