Invention Grant
- Patent Title: Scan compression architecture for highly compressed designs and associated methods
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Application No.: US15420720Application Date: 2017-01-31
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Publication No.: US10354742B2Publication Date: 2019-07-16
- Inventor: Swapnil Bahl , Shray Khullar
- Applicant: STMicroelectronics International N.V
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Slater Matsil, LLP
- Main IPC: G06F11/25
- IPC: G06F11/25 ; G11C29/32 ; G01R31/3177 ; G01R31/3185 ; G11C29/34

Abstract:
An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.
Public/Granted literature
- US20170140838A1 SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASSOCIATED METHODS Public/Granted day:2017-05-18
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