中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.022 seconds)

    SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASSOCIATED METHODS
    1.
    发明申请
    SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASSOCIATED METHODS 有权
    用于高压设计和相关方法的扫描压缩架构

    公开(公告)号：US20150323593A1

    公开(公告)日：2015-11-12

    申请号：US14270935

    申请日：2014-05-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Swapnil BAHL ,  Shray Khullar

    IPC: G01R31/3177

    CPC classification number: G11C29/32 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318547 ,  G06F11/25 ,  G11C29/34 ,  G11C2029/3202

    Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

    Abstract translation: 具有扫描压缩架构的集成电路（IC）包括耦合在测试访问输入和耦合在一起以限定多个扫描路径的IC元件（例如，触发器）的块之间的解压缩逻辑。 IC元件的块包括在每个扫描路径的初始位置处的初始数据选择器，以及在至少一个扫描路径内的附加数据选择器下游，并且被配置为重新配置至少一个中的IC元件的顺序 扫描路径。 压缩逻辑耦合在IC元件块和测试访问输出之间。

    Integrated circuit with reduced power consumption in a test mode, and related methods
    2.
    发明授权
    Integrated circuit with reduced power consumption in a test mode, and related methods 有权
    在测试模式下降低功耗的集成电路及相关方法

    公开(公告)号：US08917123B2

    公开(公告)日：2014-12-23

    申请号：US13853247

    申请日：2013-03-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Swapnil Bahl ,  Shray Khullar

    IPC: H03L7/00 ,  H03K3/012

    CPC classification number: H03K3/012 ,  G01R31/318575

    Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

    Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。

    INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, AND RELATED METHODS
    3.
    发明申请
    INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, AND RELATED METHODS 有权
    在测试模式下降低功耗的集成电路及相关方法

    公开(公告)号：US20140292385A1

    公开(公告)日：2014-10-02

    申请号：US13853247

    申请日：2013-03-29

    Applicant: STMicroelectronics International N.V.

    Inventor： SWAPNIL BAHL ,  Shray Khullar

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  G01R31/318575

    Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

    Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。

    Monitoring on-chip clock control during integrated circuit testing
    5.
    发明授权
    Monitoring on-chip clock control during integrated circuit testing 有权
    在集成电路测试期间监视片上时钟控制

    公开(公告)号：US09234938B2

    公开(公告)日：2016-01-12

    申请号：US14270964

    申请日：2014-05-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Shray Khullar ,  Swapnil Bahl

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/28

    CPC classification number: G01R31/31727 ,  G01R31/2815 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318594

    Abstract: The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.

    Abstract translation: 片内时钟（OCC）电路用于测试具有连接在扫描链中的逻辑块的集成电路。 OCC控制器被配置为接收多个时钟信号并输出​​多个移位/捕获时钟信号以供逻辑块的扫描链使用，所述多个移位/捕获时钟信号包括至少两个连续的低速捕获时钟 脉冲。 OCC监视器被配置为基于至少两个连续的在线捕获时钟脉冲来提供对OCC操作的验证。 OCC监视器可以包括多个寄存器，其被配置为基于至少两个连续的在线捕获时钟脉冲提供延迟的脉冲，配置为对延迟的脉冲之间的差异进行计数的计数器，以及耦合到计数器的输出寄存器，并被配置为 为测试工程师提供静态数据验证（例如集成电路板上的输出）。

    Synchronous on-chip clock controllers
    8.
    发明授权
    Synchronous on-chip clock controllers 有权
    同步片上时钟控制器

    公开(公告)号：US09264049B2

    公开(公告)日：2016-02-16

    申请号：US14086110

    申请日：2013-11-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Swapnil Bahl ,  Shray Khullar

    IPC: G01R31/28 ,  H03L7/06

    CPC classification number: H03L7/06 ,  G01R31/318552 ,  G01R31/318555 ,  G06F1/12

    Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

    Abstract translation: 半导体芯片包括能够同步器件上的多个时钟信号的片上时钟控制器（OCC）。 每个OCC控制器接收从一个或多个时钟发生器产生的扫描使能信号和唯一的时钟信号。 接收最慢生成时钟信号的OCC通过内部元稳定寄存器传递，并向处理较快时钟信号的OCC提供外部同步信号。 这些更快时钟的OCC可以使用外部同步信号来同步其时钟并产生测试时钟脉冲。

    SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS
    9.
    发明申请
    SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS 有权
    同步片上时钟控制器

    公开(公告)号：US20150137862A1

    公开(公告)日：2015-05-21

    申请号：US14086110

    申请日：2013-11-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Swapnil Bahl ,  Shray Khullar

    IPC: H03L7/06

    CPC classification number: H03L7/06 ,  G01R31/318552 ,  G01R31/318555 ,  G06F1/12

    Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

    Abstract translation: 半导体芯片包括能够同步器件上的多个时钟信号的片上时钟控制器（OCC）。 每个OCC控制器接收从一个或多个时钟发生器产生的扫描使能信号和唯一的时钟信号。 接收最慢生成时钟信号的OCC通过内部元稳定寄存器传递，并向处理较快时钟信号的OCC提供外部同步信号。 这些更快时钟的OCC可以使用外部同步信号来同步其时钟并产生测试时钟脉冲。

Patent Agency Ranking