Invention Grant
- Patent Title: Forming a non-planar transistor having a quantum well channel
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Application No.: US15719776Application Date: 2017-09-29
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Publication No.: US10355112B2Publication Date: 2019-07-16
- Inventor: Chi On Chui , Prashant Majhi , Wilman Tsai , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/10 ; H01L29/78 ; H01L29/165 ; H01L29/778
Abstract:
In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
Public/Granted literature
- US20180033875A1 Forming A Non-Planar Transistor Having A Quantum Well Channel Public/Granted day:2018-02-01
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