公开(公告)号：US10355112B2

公开(公告)日：2019-07-16

申请号：US15719776

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US09806180B2

公开(公告)日：2017-10-31

申请号：US14558947

申请日：2014-12-03

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US20180033875A1

公开(公告)日：2018-02-01

申请号：US15719776

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US20150084000A1

公开(公告)日：2015-03-26

申请号：US14558947

申请日：2014-12-03

Applicant: INTEL CORPORATION

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。