- Patent Title: Integrated memory assemblies comprising multiple memory array decks
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Application No.: US15797462Application Date: 2017-10-30
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Publication No.: US10366738B2Publication Date: 2019-07-30
- Inventor: Scott J. Derner , Charles L. Ingalls
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; G11C11/4091 ; G11C11/4094 ; G11C11/4097 ; G11C11/408 ; G11C11/404 ; G11C11/405 ; H01L23/528 ; H01L27/02 ; H01L49/02 ; H01L29/78

Abstract:
Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.
Public/Granted literature
- US20180218765A1 Integrated Memory Assemblies Comprising Multiple Memory Array Decks Public/Granted day:2018-08-02
Information query
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