- 专利标题: Block read count voltage adjustment
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申请号: US15799616申请日: 2017-10-31
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公开(公告)号: US10366763B2公开(公告)日: 2019-07-30
- 发明人: Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Schwegman Lundberg & Woessner, P.A.
- 主分类号: G11C16/26
- IPC分类号: G11C16/26 ; G11C16/08
摘要:
Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
公开/授权文献
- US20190130980A1 Block Read Count Voltage Adjustment 公开/授权日:2019-05-02