Invention Grant
- Patent Title: Block read count voltage adjustment
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Application No.: US15799616Application Date: 2017-10-31
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Publication No.: US10366763B2Publication Date: 2019-07-30
- Inventor: Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C16/08

Abstract:
Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
Public/Granted literature
- US20190130980A1 Block Read Count Voltage Adjustment Public/Granted day:2019-05-02
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