公开(公告)号：US12216573B2

公开(公告)日：2025-02-04

申请号：US18395363

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0891 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US11928353B2

公开(公告)日：2024-03-12

申请号：US18098279

申请日：2023-01-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G06F11/10 ,  H03M7/30

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0679 ,  G06F11/1004 ,  H03M7/6011

Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.

公开(公告)号：US11923030B2

公开(公告)日：2024-03-05

申请号：US17888641

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42 ,  G11C29/50

CPC classification number: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C29/50004 ,  G11C29/783

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

公开(公告)号：US11836392B2

公开(公告)日：2023-12-05

申请号：US17450653

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Harish R. Singidi ,  Peter Feeley

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0611 ,  G06F3/0647

Abstract: A processing device in a memory sub-system identifies a plurality of word lines at a first portion of a memory device, determines a respective error rate for each of the plurality of word lines, and determines that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold. The processing device further identifies a third word line of the plurality of word lines that is proximate to the first word line and the second word line and relocates data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.

公开(公告)号：US20230297511A1

公开(公告)日：2023-09-21

申请号：US18124447

申请日：2023-03-21

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F12/0891 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/14

CPC classification number: G06F12/0891 ,  G06F12/0811 ,  G06F12/0246 ,  G06F12/0882 ,  G06F11/14 ,  G11C16/06

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US11726867B2

公开(公告)日：2023-08-15

申请号：US17741940

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/14

CPC classification number: G06F11/1048 ,  G06F11/108 ,  G06F11/1044 ,  G06F11/1441

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US11720493B2

公开(公告)日：2023-08-08

申请号：US17581108

申请日：2022-01-21

Applicant: Micron Technology, Inc.

Inventor： Kevin R. Brandt ,  Peter Feeley ,  Kishore Kumar Muchherla ,  Yun Li ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Christopher S. Hale ,  Daniel J. Hubbard

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.

公开(公告)号：US20230230645A1

公开(公告)日：2023-07-20

申请号：US18125595

申请日：2023-03-23

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G06F12/0891 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/16 ,  G06F12/0891 ,  G11C16/26 ,  G06F2212/7211 ,  G06F2212/7201 ,  G06F2212/1016

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

公开(公告)号：US20230088790A1

公开(公告)日：2023-03-23

申请号：US18070844

申请日：2022-11-29

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Kulachet Tanpairoj ,  Peter Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe

IPC: G06F12/02 ,  G06F3/06

Abstract: A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

公开(公告)号：US11593261B2

公开(公告)日：2023-02-28

申请号：US17374906

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0891 ,  G06F3/06 ,  G06F12/06 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.