Invention Grant
- Patent Title: Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
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Application No.: US15575283Application Date: 2015-06-26
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Publication No.: US10366903B2Publication Date: 2019-07-30
- Inventor: Kevin Lin , Robert Lindsey Bristol , Alan M. Myers
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/038145 WO 20150626
- International Announcement: WO2016/209293 WO 20161229
- Main IPC: H01L21/32
- IPC: H01L21/32 ; H01L21/3213 ; H01L21/768 ; H01L23/522 ; H01L21/033

Abstract:
Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
Public/Granted literature
- US20180158694A1 TEXTILE PATTERNING FOR SUBTRACTIVELY-PATTERNED SELF-ALIGNED INTERCONNECTS, PLUGS, AND VIAS Public/Granted day:2018-06-07
Information query
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