Invention Grant
- Patent Title: Wire bonding between isolation capacitors for multichip modules
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Application No.: US15857234Application Date: 2017-12-28
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Publication No.: US10366958B2Publication Date: 2019-07-30
- Inventor: Thomas Dyer Bonifield , Jeffrey Alan West , Byron Lovell Williams
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: B81B7/00
- IPC: B81B7/00 ; H01L23/00 ; H01L23/64 ; H01L25/00 ; H01L27/07 ; H01L49/02 ; H01L25/065

Abstract:
A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
Public/Granted literature
- US20190206812A1 WIRE BONDING BETWEEN ISOLATION CAPACITORS FOR MULTICHIP MODULES Public/Granted day:2019-07-04
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