Invention Grant
- Patent Title: Single event upset (SEU) mitigation for FinFET technology using fin topology
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Application No.: US15087947Application Date: 2016-03-31
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Publication No.: US10366999B2Publication Date: 2019-07-30
- Inventor: Pierre Maillard
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Keith Taboada
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L29/08 ; H01L29/78 ; H01L27/088 ; H01L27/092
Abstract:
Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
Public/Granted literature
- US20170287919A1 SINGLE EVENT UPSET (SEU) MITIGATION FOR FINFET TECHNOLOGY USING FIN TOPOLOGY Public/Granted day:2017-10-05
Information query
IPC分类:
