Invention Grant
- Patent Title: CVD silicon monolayer formation method and gate oxide ALD formation on semiconductor materials
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Application No.: US15727351Application Date: 2017-10-06
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Publication No.: US10373824B2Publication Date: 2019-08-06
- Inventor: Andrew C. Kummel , Mary Edmonds , Mei Chang , Jessica S. Kachian
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Main IPC: C23C16/24
- IPC: C23C16/24 ; H01L21/02

Abstract:
Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1−xAs, InxGa1−xSb, InxGa1−xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.
Public/Granted literature
- US20180033610A1 CVD SILICON MONOLAYER FORMATION METHOD AND GATE OXIDE ALD FORMATION ON SEMICONDUCTOR MATERIALS Public/Granted day:2018-02-01
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